The present invention relates to a pad circuit disposed in an integrated circuit chip and a related operating method, and more particularly to a pad circuit and a related operating method for automatically adjusting the gain of the pad circuit for the integrated circuit chip.
An integrated circuit chip is inevitable to process and transmit a number of data signals today. Due to the increase of processing and transmission speeds and the decrease of rated operational voltage, the driving efficiency of a pad circuit becomes more and more significant than before. FIG. 1A is a schematic diagram illustrating the position of a pad circuit 12 in an integrated circuit (IC) chip 1, wherein the pad circuit 12 operates between a core logic circuit 10 and an input/output pin 11 in the IC chip 1. FIG. 1B schematically shows the pad circuit 12 cooperating with the input/output pin 11. When a signal output operation is activated, an output enable (OE) signal enables an output buffer 121 to output a signal from the core logic 10 via the output buffer 121 and the input/output pin 11. On the contrary, when the signal input operation is activated, the OE signal disables the output buffer 121 so as to input a signal to the core logic circuit 10 via the input/output pin 11 and an input buffer 122.
Generally, the output load of the IC chip regarding the input/output pin 11 may vary with the configurations of the hardware devices driven thereby. For example, an integrated drive electronics (IDE) bus may be shared by various number and configurations of hard disk drives or optical disk drives. In order to meet different load requirements resulting from different hardware configurations, the output buffer 121 is manually set up to a proper gain according to the expected load before delivery for assuring of sufficient driving power from the input/output pin 11. However, the preset gain is not adapted to all possible hardware configurations to output perfect driving power any time. The computer system may operate abnormally when the hardware configuration established by the user is beyond the range covered by the preset gain.
Moreover, for an IC chip having many pad circuits, some signal levels on the pad circuits that should be maintained at their current ones may be abnormally switched when a lot of pad circuits simultaneously change their levels. For example, when a signal xe2x80x9c00011100xe2x80x9d on an 8-bit bus being switched to xe2x80x9c00001000xe2x80x9d, it is obvious that the fifth bit does not need to change its current signal level. However, the neighboring signal lines of the fifth bit (that is, the fourth and the sixth signal lines) must be switched from logic 1 to logic 0, which may affect the fifth bit to be abnormally switched from logic 1 to 0 (i.e., xe2x80x9c00000000xe2x80x9d will appear on the 8-bit bus) sometimes. Additionally, the statuses of the signal lines, including the trace lengths or the employed materials of the signal lines, or even the connection statuses of the terminal devices (e.g., the pin connection statuses of a hard disk), are varied as environments and applications, which may usually cause unexpected malfunctions to the computer system. Unfortunately, the outside environments regarding bus or connection statuses are difficult to adjust since they are different as applications. Therefore, the purpose of the present invention is to develop a pad circuit with adjustable gain, and a method for automatically adjusting gain for a pad circuit applied in an integrated circuit chip to deal with the above situations encountered in the prior art.
An object of the present invention is to provide a pad circuit with adjustable gain and a method for automatically adjusting gain for a pad circuit applied in an integrated circuit chip for selecting proper gains in response to various hardware configurations.
According to an aspect of the present invention, there is provided a pad circuit for use in an integrated circuit chip including a core logic circuit. The pad circuit includes an input/output pin, a gain-adjustable output buffer coupled between the core logic circuit and the input/output pin for adjusting the energy of an output signal from the core logic circuit and then outputting the output signal to external devices via the input/output pin. An input buffer of the circuit pad is coupled between the input/output pin and the core logic circuit for receiving an input signal from the external devices via the input/output pin and then outputting the input signal to the core logic circuit. A signal feature detector in the circuit pad is coupled to an output end of the input buffer and the gain-adjustable output buffer for receiving a feedback test signal from the external device via the input buffer after a test signal is processed by the gain-adjustable output buffer and outputted to the external devices via the input/output pin. The signal feature detector still realizes a test result in response to a waveform feature of the feedback test signal. The gain-adjustable output buffer adjusts gains according to the test result.
Preferably, the signal feature detector comprises a rising edge detector coupled to the output end of the input buffer for comparing a maximum value of the feedback test signal with a first voltage threshold to obtain a first portion of the test result. A falling edge detector in the signal feature detector is coupled to the output end of the input buffer and the gain-adjustable output buffer for comparing a minimum value of the feedback test signal with a second voltage threshold to obtain a second portion of the test result.
In an embodiment, the rising and falling edge detectors can be implemented by flip-flops.
In an embodiment, the signal feature detector is further coupled to a register, which is coupled to the rising and falling edge detectors, respectively, for storing the test result. Preferably, the pad circuit further includes a discriminating and adjusting device coupled to the register and the gain-adjustable output buffer for adjusting the gain of the gain-adjustable output buffer according to the test result.
Preferably, the pad circuit further includes a reset signal input end coupled to the signal feature detector for receiving a reset signal therefrom to reset the signal feature detector.
Preferably, the pad circuit gain-adjustable output buffer further includes an enable end that couples to the core logic circuit for enabling the gain-adjustable output buffer in response to an enable signal so that the output signal can be transmitted to the external devices via the input/output pin. Preferably, the gain-adjustable output buffer is further coupled to a multiplexer including five input ends and two output ends. These five input ends are used for receiving a test-enable signal, an operation-enable signal, the test signal, an operation signal and a switch signal, respectively. The two output ends are coupled to an input end of the gain-adjustable output buffer and the enable end. The multiplexer is controlled by the switch signal to select one set of signals from the test-enable/test signals and the operation-enable/operation signals to be the output for feeding into to the gain-adjustable output buffer via the input end and the enable end, respectively.
According to another aspect of the present invention, there is provided a method for automatically adjusting the gain of a pad circuit in an integrated circuit chip. The integrated circuit chip includes a core logic circuit and the pad circuit includes an input/output pin, a gain-adjustable output buffer and an input buffer. The method includes the steps of outputting a test signal from the core logic circuit to the gain-adjustable output buffer for being processed and then outputted to external devices via the input/output pin; receiving a feedback test signal to the input buffer from the external device; realizing a test result according to a waveform feature of the feedback test signal; and adjusting the gain of the gain-adjustable output buffer according to the test result.
Preferably, the test result is realized by the steps as follows. A maximum value of the feedback test signal is firstly compared with a first voltage threshold to obtain a first portion of the test result, which is a first logic value when the maximum value of the feedback test signal is larger than the first voltage threshold, and a second logic value when the maximum value is not larger than the first voltage threshold. Next, a minimum value of the feedback test signal is compared with a second voltage threshold to obtain a second portion of the test result, which is the first logic value when the minimum value of the feedback test signal is smaller than the second voltage threshold, and the second logic value when the minimum value of the fed-back test signal is not smaller than the second voltage threshold.
In an embodiment, the test signal is switched from a low level to a high one under a waveform rising operation in a first time period. In the first time period, a driving condition is determined to be bad when both the first portion and second portion of the test result are indicated to be the first logic value. A driving condition is determined to be good when the first portion and the second portion of the test result are indicated to be the first logic value and the second logic value, respectively. A driving condition is determined to be abnormal when the first portion of the test result is indicated to be the second logic value. Once the driving condition is determined to be bad or abnormal, a new gain value is given to the gain-adjustable output buffer for re-adjusting the gain once again.
In another embodiment, the test signal is switched from high to low under a waveform falling operation in a second time period, wherein a driving condition is determined to be bad when both the first and the second portions of the test result are indicated to be to the first logic value. A driving condition is determined to be good when the first portion and the second portion of the test result are indicated to be the first logic value and the second logic value, respectively. A driving condition is determined to be abnormal when the second portion of the test result is indicated to be the second logic value. Once the driving condition is bad or abnormal, a new gain value will be given to the gain-adjustable output buffer for re-performing a further test.
Preferably, the first logic value represents logic 1 and the second logic value represents logic 0.
According to a further aspect of the present invention, there is provided a method for automatically adjusting the gain of a plurality of pad circuits in an integrated circuit chip, wherein the integrated circuit chip includes a core logic circuit. Any one of the pad circuits includes an input/output pin, a gain-adjustable output buffer and an input buffer. The method includes the steps of outputting parallel test signals from the core logic circuit to the gain-adjustable output buffers for being processed and then outputted via the input/output pins; feeding feedback parallel test signals back into the input buffers; realizing a set of test results according to waveform features of the feedback parallel test signals; and adjusting respective gains of the gain-adjustable output buffers according to the set of test results.
Preferably, each of the test results is realized by the steps as follows. Firstly, a maximum value of any feedback parallel test signal is compared with a first voltage threshold to obtain a first portion of the test results, which is a first logic value when the maximum value of the feedback parallel test signal is larger than the first voltage threshold, and a second logic value when the maximum value is not larger than the first voltage threshold. A minimum value of the feedback parallel test signal is then compared with a second voltage threshold to obtain a second portion of the corresponding test result, which is the first logic value when the minimum value of the feedback test signal is smaller than the second voltage threshold, and the second logic value when the minimum value of the feedback test signal is not smaller than the second voltage threshold.
Preferably, a waveform rising operation is performed to rise the signal level of the test signals in a first time period and a falling operation is performed to drop the signal level of the test signals in a second time period. In the first time period, a driving condition of a pad circuit is determined to be bad when both the first portion and second portion of the test results are indicated to be the first logic value, the driving condition of the pad circuit is determined to be good when the first portion and second portion of the test result are respectively the first logic value and the second logic value, and the driving condition of the pad circuit is determined to be abnormal when the first portion of the test result is the second logic value. On the other hand, in the second time period, a driving condition of the pad circuit is determined to be bad when both the first portion and second portion of the test result are the first logic value, the driving condition of the one of the pad circuits is determined to be good when the first portion and second portion of the corresponding test result are respectively the first logic value and the second logic value, and the driving condition of the pad circuit is determined to be abnormal when the first portion of the test result is the second logic value. Preferably, a new gain value for the gain-adjustable output buffer is entered for a further test when the driving condition is bad or abnormal in the first or second time periods.